(1) Field of the Invention
The present invention relates to a method used to fabricate a capacitor structure for a dynamic random access memory, (DRAM) device, and more specifically to a method used to form a capacitor structure, featuring a hemispherical grain, (HSG), polysilicon layer.
(2) Description of the Prior Art
The semiconductor industry is continually striving to improve device performance, while still focusing on methods of reducing manufacturing costs. These objectives have been successfully addressed by the ability of the semiconductor industry to produce chips with sub-micron features, or micro-miniaturization. Sub-micron features allow the reduction in performance degrading capacitances and resistances to be realized. In addition the smaller features result in a smaller chip, however still possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller, or sub-micron features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 64 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area for placement of overlying STC structures.
One method of maintaining, or increasing STC capacitance, while still decreasing the lateral dimension of the capacitor, has been the use of rough, or hemispherical grain, (HSG), polysilicon layers. HSG polysilicon layers have been used as an overlying layer, on a conventional polysilicon structure, as shown by Dennison, in U.S. Pat. No. 5,340,763, and by Nagasawa, et al, in U.S. Pat. No. 5,444,653. The convex and concave features of the HSG polysilicon layer result in increases in capacitor surface area, without consuming additional device area, thus resulting in DRAM capacitance increases, when compared to counterparts fabricated with smooth capacitor surfaces. However several factors have limited the use of HSG layers, for DRAM applications. The presence of an unwanted thin native oxide, on an underlying polysilicon capacitor surface, can result in poor adhesion between the subsequent HSG polysilicon layer, and the underlying polysilicon capacitor. To alleviate the effect of the thin native oxide a high vacuum, in situ cleaning procedure, has to be used prior to HSG polysilicon deposition. In addition to increase the roughness feature of an HSG polysilicon layer, the dopant level of the HSG layer is maintained at a lower level than the dopant concentration in the underlying polysilicon capacitor. The dopant gradient established between the low dopant HSG polysilicon layer, and the higher dopant, underlying polysilicon capacitor, results in a capacitance depletion phenomena, reducing the advantage of the capacitance increase realized from the roughened surface HSG polysilicon layer. Again an additional processing step, a plasma treatment, is used to increase the dopant concentration in the HSG polysilicon layer.
This invention will describe a process for creating an HSG polysilicon layer, featuring improved adhesion between HSG polysilicon and the underlying polysilicon capacitor surface, and also featuring a reduction in the capacitance depletion phenomena. The HSG polysilicon layer, used in this invention results in the improved characteristics via the use of a thin, overlying, highly doped polysilicon layer, thus avoiding the use of a high vacuum, in situ clean, prior to HSG polysilicon deposition, as well as avoiding the additional plasma treatment, applied post HSG polysilicon deposition.